1. Technical Field of the Invention
The present invention relates generally to an input interface circuit for a semiconductor integrated circuit device which is designed to protect circuit elements against an undesirable input of voltage higher than that of a power supply.
2. Background Art
FIG. 5 illustrates a typical input interface circuit for an integrated circuit device that uses CMOS logic. The input interface circuit is designed especially for withstanding a high voltage input and has an input terminal 1 coupled with drains of a P-channel MOSFET 2 and an NMOSFET 3. The FETs 2 and 3 are kept at high and low levels, respectively, when the input interface circuit is in service. Parasitic diodes 2a and 3a are provided between a source and a drain of the FET 2 and between a drain and a source of the FET 3 respectively.
To the input terminal 1, gates of a P-channel MOSFET 4 and an NMOSFET 5 are coupled. The FETs 4 and 5 are also coupled at drains thereof with an input terminal of an inverter gate 6 that is an internal element of an IC. A resistor 7 is connected in series with the input terminal 1 and serves as a current limiter.
The parasitic diodes 2a and 3a disposed at the first stage of the input interface circuit work as protective elements for clamping the high voltage applied to the input terminal 1. The FETs 2 and 3 are turned on in response to input of negative and positive surge voltages to the input terminal 1 and work as protective elements for absorbing the surge voltages on a power supply side and a ground side. The FETs 2 and 3 also serve as an output interface when an output signal is supplied to gates thereof from an internal circuit.
The input interface circuit thus constructed may be used in an input circuit of an ECU (Electronic Control Unit) for automotive vehicles. In general, the voltage of a storage battery installed in automotive vehicles is between 12V and 14V. Therefore, in a case of use in an automotive vehicle, the input interface circuit is generally designed to operate on 5V that is provided by the battery voltage. An input signal to the ECU has the voltage equal to the battery voltage. In order to protect the ECU against a high level signal (e.g., +12V signal) inputted to the input terminal 1, the protection circuit made up of the parasitic diodes 2a and 3a works to clamp it at the voltage that is the sum of the power supply voltage and VF (=a forward voltage of the diode 2a). In this condition, a high electric field acts on an oxide layer on the gate of each of the FETs 3 and 5.
Assuming that the voltage of the power supply is 5V, and the forward voltage VF of the diode 2a is 1V, an oxide layer of a gate of a 5V-FET is generally formed, as shown in FIG. 6(a), to have a thickness on the order of 150 angstrom (i.e., 15 nm). The application of 6V (=voltage of power supply+VF) to the 5V-FET will cause an electric field of 4 MV/cm to be produced which acts on the 5V-FET. The electric field of 4 MV/cm is generally thought of as the limit of service life of an oxide layer. The application of an electric field of more than 4 MV/cm to the oxide layer for a long time may thus cause the oxide layer to break down. In order to avoid this problem, the oxide layer of the gate of each of the FETs 3 and 5 is formed to have a thickness of about 200 angstrom (i.e., 20 nm), as shown in FIG. 6(b), so that an electric field of 3 MV/cm is produced when a voltage of 6V is applied thereto.
However, the formation of FETs whose oxide layers are different from each other on a semiconductor substrate together requires an additional process of increasing the thickness of the oxide layers selectively using a glass mask. Additionally, the difference in thickness between the oxide layers of the FETs will cause threshold voltages to be different from each other, thus requiring an ion implantation process for adjustment of the threshold voltages.
Further, when signals are transmitted between ICs whose ground potentials are different from each other, a negative high voltage may be applied to the input terminal 1, which causes a high electric field to act on the power supply side FETs 2 and 4. The same measures as described above are, thus, required.
It is therefore a principal object of the invention to avoid the disadvantages of the prior art.
It is another object of the invention to provide a high voltage-withstanding structure of an input interface circuit for a semiconductor integrated circuit device which may be made in simple processes.
According to one aspect of the invention, there is provided an input interface circuit for a semiconductor integrated circuit device. The input interface circuit comprises: (a) a pair of diodes provided between a power supply and an outside input terminal and between the outside input terminal and ground, respectively; (b) a first and a second PMOSFET connected in series between the power supply and an inside input terminal coupled to an internal circuit element of the semiconductor integrated circuit device; (c) a first and a second NMOSFET connected in series between ground and the inside input terminal; (d) a third PMOSFET connected in series between the outside input terminal and a gate of the first PMOSFET; (e) a third NMOSFET connected in series between the outside input terminal and a gate of the second NMOSFET; and (f) an intermediate voltage source applying a voltage which is intermediate between ground potential and a voltage of the power supply to a gate of each of the first NMOSFET, the second PMOSFET, the third PMOSFET, and the third NMOSFT.
In the preferred mode of the invention, the two diodes are parasitic diodes provided by the third NMOSFET and the third PMOSFET.
A fourth PMOSFET is provided which is connected in series with the third PMOSFET between the outside input terminal and the power supply, A fourth NMOSFET is provided which is connected in series with the third NMOSFET between the outside input terminal and ground. The fourth PMOSFET and NMOSFET are kept turned off at all times. The parasitic diodes are coupled in series with the third and fourth PMOSFETs and the third and fourth NMOSFETs, respectively.
A plurality of protective MOSFETs are further provided each of which is coupled at a gate thereof to one of output side terminals thereof. Each of the protective MOSFETs is turned on when a high voltage is applied to a circuit line of the input interface circuit placed in a high impedance state to work to have the high voltage escape to the intermediate voltage source.
The voltage applied to the gates of the PMOSFETs is lower than that to the respective gates of the NMOSFETs.
The input interface circuit also includes a first and a second protective MOSFET. The first protective MOSFET is connected between the outside input terminal and the power supply. The second protective MOSFET is connected between ground and the outside input terminal.